The present invention relates to a semiconductor storage device employing a hierarchical bit lining method and executing a serial access to memory cells connected with the same word line.
Existing semiconductor storage devices having a large capacity to be used in an image data-processing field include those which operate under a so-called serial access mode, i.e., execute a serial access to memory cells connected with the same word line.
FIG. 6 is a block diagram showing the construction of a conventional read-only semiconductor storage device (ROM: read-only memory) executing a serial access operation. The semiconductor storage device has a 16-megabit storage capacity; an input address is of 20 bits (A0-A19) and output data is of 16 bits (D0-D15).
As shown in FIG. 6, the semiconductor storage device has memory cell arrays MA0, . . . , MAm, . . . arranged in a row direction, each memory cell array consisting of memory cells M arranged in a matrix shape. The semiconductor storage device further has a row decoder RD for outputting a row selection signal Sr upon receipt of a row address signal (A8-A19) through an address buffer Abuf1, and a row selector X-S5 for selecting one word line from a plurality of word lines WLi (i=0-4095) upon receipt of the row selection signal Sr from the row decoder RD. The semiconductor storage device further has a column decoder CD for outputting a column selection signal Sc upon receipt of a column address signal (A0-A7) through an address buffer Abuf2, and a plurality of column selectors Y-S2 each for selecting one bit line from a plurality of bit lines MB0-MB255 of the associated memory cell array MA0, . . . , MAm, . . . upon receipt of the column selection signal Sc from the column decoder CD. Sense amplifiers SA0, . . . , SAm, . . . for detecting information of each memory cell M are connected with the column selectors Y-S2, respectively. Detection signals DS0, . . . , DSm, . . . of the respective sense amplifiers SA0, . . . , SAm, . . . are transmitted to output circuits Obuf0, . . . , Obufm, . . . , and output as signals D0, . . . , Dm, . . . .
Supposing that memory cells selected by one word line WLi constitute a page and that a plurality of bits within one page which can be accessed simultaneously constitute a word, one page consists of 256 words specified by the column address (A0-A7) in the input addresses (A0-A19).
The serial access operation of the semiconductor storage device is described below with reference to a timing chart shown in FIG. 7.
After the level of each bit of the address signal (A0-A19) becomes definite at a time t10, the row decoder RD outputs the row selection signal Sr corresponding to a page (Ph) to the row selector X-S5, upon receipt of the row address signal (A8-A19) shown in FIG. 7 (a) from the address buffer Abufl. Upon receipt of the row selection signal Sr from the row decoder RD, the row selector X-S5 selects one word line WLi. As a result, the level of the word line signal of the word line WLi becomes "High" slowly (in FIG. 7 (c)). At a time t11, data DmBk (m=0-15, k=0-255) of a bit line MBj of each of the memory cell arrays MA0, . . . , MAm, . . . becomes definite (FIG. 7 (d)). Before the time t11, upon receipt of the column address signal (A0-A7) (shown in FIG. 7(b)) through the address buffer Abuf2, the column decoder CD outputs the column selection signal Sc to the column selectors Y-S2 (FIG. 7 (e)).
Upon receipt of the column selection signal Sc from the column decoder CD, each column selector Y-S2 selects one bit line from among the bit lines MB0-MB255 of each of the memory cell arrays MA0, . . . , MAm, . . . . As a result, at a time t12, the level of each of the output signals D0, . . . , Dm, . . . of word data Wo corresponding to the column address signal (A0-A7) becomes definite (FIG. 7 (f)). Then, the column selection signal changes in level in consequence of the change in level of only the column address signal (A0-A7) at a time T13. As a result, the levels of the output signals DO, . . . , Dm, . . . of word data W1 promptly become definite at a time t14 because one word line has been already selected from among the word lines WLi.
With the change of the value of the column address signal (A0-A7) from 0 to 255, the data DmBk (m=0-15, k=0-255) of one page (Ph), namely, word data W0-W255 are serially read. When the page changes from (Ph) to a subsequent one (Ph+1), the current word line WLi is changed to another one WLi. In a similar manner, word data W0-W255 are serially read.
In the reading operation of the semiconductor storage device having the serial access mode, a plurality of memory cells of each of the memory cell arrays MA0, . . . , MAm, . . . are simultaneously selected according to the column address signal (A0-A7) and the row address signal (A8-A19). Then, when the plurality of data are read as the page data by the sense amplifiers SA0, . . . , SAm, . . . , the levels of each bit of the column address signal (A0-A7) are changed so that the data DmBk (m=0-15, k=0-255) of the selected memory cells are switched at a high speed and output serially. When changing the row address signal (A8-A19), it takes a long time for output data to become definite because it takes a long time to change the word line s WLi. On the other hand, when changing only the column address signal (A0-A7), a high-speed reading operation is executed in the serial access mode because only the time for the column decoder RD2 to switch one column selection signal to another and the response time of the sense amplifiers SA0, . . . , SAm, . . . are necessary.
There is known a semiconductor storage device employing a so-called hierarchical bit lining method in which bit lines are composed of main bit lines and sub-bit lines in a hierarchical structure so that the semiconductor storage device has a high density (Laid-Open Japanese Patent Publication No. 4-311900). It is also known to apply the hierarchical bit lining method to a semiconductor storage device which executes the serial access operation.
FIGS. 8 and 9 show an example of a hierarchical bit lining semiconductor storage device operable in the serial access mnode. FIG. 8 shows a circuit of one block of a memory cell array of the semiconductor storage device. Parts shown in FIGS. 8 and 9 similar to those in FIG. 6 are denoted by the same reference numerals as those of FIG. 6. In the semiconductor storage device, sources or drains of a plurality of memory cells Mxy arranged in a column direction are connected with sub-bit lines SB0, SB1, . . . . As shown in FIG. 8, each two of the alternate sub-bit lines SB0, SB2, . . . starting from the first one on the left-hand side of the figure are connected with each of the alternate main bit lines MB0, MB2, . . . starting from the first one, through bank selection transistors TB00, TB10, . . . . Similarly, each two of the other alternate sub-bit lines SB1, SB3, . . . starting from the second on the left-hand side of the figure are connected with each of the other alternate main bit lines MB1, MB3, . . . through bank selection transistors TB20, TB30, . . . . A bank selection line BS0 connected with the gate of each of the bank selection transistors TB00, TB01, . . . is parallel with word lines WLi, and a bank selection line BS1 connected with the gate of each of the bank selection transistors TB10, TB11, . . . is also parallel with the word lines WLi. A bank selection line BS2 connected with the gate of each of the bank selection transistors TB20, TB21, . . . is parallel with the word lines WLi, and a bank selection line BS3 connected with the gate of each of the bank selection transistors TB30, TB31, . . . is also parallel with the word lines WLi.
As shown in FIG. 9, each of memory cell arrays MA0, . . . , MAm, . . . , MA15 is composed of a plurality of blocks 0-255 (each of which is constructed as shown in FIG. 8) arranged in a column direction. The memory cells of the blocks 0-255 in the same columns are connected with the common main bit lines MB0, MB1, . . . extending in the column direction through the common sub-bit lines SB0, SB1, . . . and the bank selection transistors TB00, TB10, . . . . The main bit lines MB0, MB1, . . . are connected with associated column selectors Y-S9.
The hierarchical bit lining semiconductor storage device operates in the serial access mode as follows: In selecting a memory cell M1 from among memory cells M0, M1, M2, and M3 connected with the word line WL1, for example, input of an address makes the row selector X-S9 select one word line WLi. As a result, the level of the word line signal of the word line WLi becomes "High", and the level of the bank selection signal of each of the bank selection lines BS0 and BS2 becomes "High". In this manner, the memory cells M0, M1, . . . whose gates are connected with the word line WL1 are selected, and the bank selection transistors TB00 and TB20 are turned on to thereby connect the sub-bit lines SB1 and SB2 with the main bit lines MB1 and MB0, respectively. As a result, the memory cell M1 whose source and drain are connected with the sub-bit lines SB1 and SB2 is selected. Then, based on the inputted address, the level of the column selection signal of the column selection line CS0 is turned "High" by the operation of the column selector Y-S9, and a column selection transistor TR0 in the column selector Y-S9 is turned on. When the column selection transistor TR0 is turned on, the memory cell M1 is connected with a sense amplifier (not shown) through the sub-bit line SB2 and the main bit line MB0. Because the main bit line MB1 is connected with the ground potential serving as a reference potential, a signal DC0 indicating the information of the memory cell M1 is input to the sense amplifier. In a similar manner, a memory cell M1 of each of the remaining memory cell arrays MA2, . . . , MAm, . . . , MA15 is selected, and signals DC2, . . . , DCm, . . . , DC15 each indicating the information of the memory cell M1 of each of the memory cell arrays MA2, . . . , MAm, . . . , MA15 is input to the respective sense amplifiers (not shown).
In the semiconductor storage device employing the hierarchical bit lining method and executing the serial access operation, the number of times of switching the bank selection lines BS0-BS3 is considerably larger than that of the word lines WLi. Thus the average access time depends on the transition time (ie, a time required for the change from an active state to an inactive state and vice versa) of the bank selection line signals of the bank selection lines BS0-BS3. Therefore, when increasing the number of serially accessible memory cells, ie, memory cells whose data can be serially read by the serial access mode operation of the semiconductor storage device, a load is increasingly applied to the circuit for driving the bank selection lines BS0-BS3. As a result, the transition time of the bank selection line signals of the bank selection lines BS0-BS3 increases, which makes the average access time longer accordingly.